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ultra-compact high performance serial real-time clock ics RS5C317A/b electronic devices division no.ea-036-9908 application manual
no tice 1. the products and the product specifications described in this application manual are subject to change or dis - continuation of production without notice for reasons such as improvement. therefore, before deciding to use the products, please refer to ricoh sales representatives for the latest information thereon. 2. this application manual may not be copied or otherwise reproduced in whole or in part without prior written con - sent of ricoh. 3. please be sure to take any necessary formalities under relevant laws or regulations before exporting or other - wise taking out of your country the products or the technical information described herein. 4. the technical information described in this application manual shows typical characteristics of and example application circuits for the products. the release of such information is not to be construed as a warranty of or a grant of license under ricoh's or any third party's intellectual property rights or any other rights. 5. the products listed in this document are intended and designed for use as general electronic components in standard applications (office equipment, computer equipment, measuring instruments, consumer electronic products, amusement equipment etc.). those customers intending to use a product in an application requiring extreme quality and reliability, for example, in a highly specific application where the failure or misoperation of the product could result in human injury or death (aircraft, spacevehicle, nuclear reactor control system, traffic control system, automotive and transportation equipment, combustion equipment, safety devices, life support system etc.) should first contact us. 6. we are making our continuous effort to improve the quality and reliability of our products, but semiconductor products are likely to fail with certain probability. in order prevent any injury to persons or damages to property resulting from such failure, customers should be careful enough to incorporate safety measures in their design, such as redundancy feature, fire-containment feature and fail-safe feature. we do not assume any liability or responsibility for any loss or damage arising from misuse or inappropriate use of the products. 7. anti-radiation design is not implemented in the products described in this application manual. 8. please contact ricoh sales representatives should you have any questions or comments concerning the prod - ucts or the technical information. june 1995
outline ...................................................................................................... 1 fea tures .................................................................................................... 1 block dia gram ......................................................................................... 2 applica tions ............................................................................................. 2 pin configura tion ................................................................................... 2 pin descriptions ...................................................................................... 3 absolute maximum ra tings ................................................................... 4 recommended opera ting conditions ................................................. 4 dc chara cteristics ................................................................................ 5 a c chara cteristics ................................................................................ 5 timing char ts ........................................................................................... 6 functional descriptions ...................................................................... 7 1. addressing ................................................................................................. 7 2. registers ................................................................................................... 8 3. counters .................................................................................................. 14 usa ges ...................................................................................................... 16 1. read data (f or the RS5C317A) ...................................................................... 16 2. wr ite data (f or the RS5C317A) ....................................................................... 17 3. read data (f or the rs5c317b) ...................................................................... 18 4. wr ite data (f or the rs5c317b) ....................................................................... 19 5. ce pin .................................................................................................... 20 6. configur ation of oscillating circuit .................................................................... 21 7. oscillator halt sensing ................................................................................. 22 8. t ypical p o w er supply circuit ........................................................................... 23 9. oscillation f requency adjustment ..................................................................... 23 10. interr upt oper ation .................................................................................... 25 RS5C317A/b applica tion manu al contents
11. timer .................................................................................................... 27 12. 32khz cloc k output ................................................................................... 27 13. t ypical application ..................................................................................... 28 14. t ypical char acter istic measurements ............................................................... 29 15. t ypical softw are-based oper ations ................................................................. 31 p a cka ge dimensions .............................................................................. 35 t aping specifica tion .............................................................................. 35
ul tra-comp a ct high performance serial real-time clock ics 1 RS5C317A/b outline the RS5C317A/b are cmos type real-time clock ics which are connected to the cpu via three signal lines and capable of serial transmission of clock and calendar data to the cpu. the RS5C317A/b can generate various periodic interrupt clock pulses lasting for long period (one month), further alarm interrupt can be made by days of the week, hours, and minutes. the function of 32khz clock output and timer counter for watch-dog-timer are also include. driving an oscillation circuit at constant voltage, the circuit undergoes few voltage fluctuations and consequently realizes low current consumption (0.6 a at 3v). it also provides an oscil - lator halt sensing function for application to data validity at power-on and other occasions. integrated into a compact and thin 14pin ssop (0.65mm pitch), the RS5C317A/b are the optimum choice for equipment requiring small size and low power consumption. the RS5C317A and the rs5c317b reads/writes data at falling and rising edge of serial clock respectively. time keeping voltage 1.6v to 6.0v lowest supply current 0.6 a typ. (1.5 a max.) at 3v connection to the cpu via only three pins: ce, sclk/sclk and sio for addressing and data read/write a clock counter (counting hours, minutes, and seconds) and a calendar counter (counting leap years, years, months, days, and days of the week) in bcd code periodic interrupt pulses to the cpu with cycles ranging from one month to 1/1024hz, with interrupt flags and interrupt halt alarm interrupt (days of the week, hours, minutes) counter for timer with internal clock oscillator halt sensing to judge internal data validity 32khz clock output with enable switch second digit adjustment by 30 seconds 12-hour or 24-hour time display selectable automatic leap year recognition up to the year 2099 cmos logic package: 14pin ssop (0.65mm pitch) fea tures
RS5C317A/b 2 applica tions communication equipment (multi-function telephone, portable telephone, phs, pager) business machine (facsimile, portable facsimile) personal computer (desktop type, notebook type, word processor, pda, electronic notebook, tv games) audio visual equipment (portable audio equipment, video camera, camera, digital camera, remote control equip - ment) home use (rice cooker, microwave range) pin configura tion ?14pin ssop (0.65mm pitch) c e 1 v d d s c l k 3 2 k o u t s i o n c c l k c o s c i n a l r m o s c o u t t m o u t n c v s s i n t r r s 5 c 3 1 7 a r s 5 c 3 1 7 b 1 4 2 1 3 3 1 2 4 1 1 5 1 0 6 9 7 8 c e 1 v d d s c l k 3 2 k o u t s i o n c c l k c o s c i n a l r m o s c o u t t m o u t n c v s s i n t r 1 4 2 1 3 3 1 2 4 1 1 5 1 0 6 9 7 8 block dia gram o s c d i v a d d r e s s d e c o d e r a d d r e s s r e g i s t e r t i m e c o u n t e r ( s e c , m i n , h o u r , w e e k , d a y , m o n t h , y e a r ) i n t e r r u p t c o n t r o l s h i f t r e g i s t e r i / o c o n t r o l o s c d e t e c t o s c i n o s c o u t c l k c 3 2 k o u t 3 2 k h z o u t p u t c o n t r o l a l a r m r e g i s t e r ( w e e k , m i n , h o u r ) c o m p a r a t o r s i o s c l k / s c l k * c e i n t r a l r m t m o u t * ) RS5C317A: sclk rs5c317b: sclk
RS5C317A/b 3 pin no. 1 2 3 8 5 6 11 10 13 4 14 7 9, 12 pin description s symbol ce sclk (a type) sclk (b type) sio intr alrm tmout oscin oscout 32kout clkc vdd vss nc name chip enable input shift clock input serial input/output interrupt output alarm output timer output oscillator circuit input/output 32khz output control input for 32khz output positive/negative power supply input no connection description the ce pin is used to interface the cpu and is accessible when held at the high level. this pin is connected to a pull-down resistor. it should be switched to the low level or opened when not accessed or when powering off the system. holding the ce pin high for more than 2.5 seconds forces 1hz interrupt pulses to be output from the intr pin for oscillation frequency measurement. (no ?hz pulse?is out - put for less than 1.5 seconds.) this pin is used to input shift clock pulses to synchronize data input to, and output from, the sio pin. sclk and sclk are for writing data at falling and rising edge of clock pulses respectively and also reading data at rising and falling edge of clock pulses respectively. the sio pin inputs and outputs written or read data in synchronization with shift clock pulses from the sclk/sclk pin. the sio pin causes high impedance when ce pin is held at the low level (cmos input/output). after the ce pin is switched to the high level and the control bits and the address bits are input from the sio, the sio pin performs serial input and output operations. the intr pin outputs periodic interrupt pulses and alarm interrupt to the cpu. this pin functions as an nch open drain output even when the ce pin is held at the low level. the alrm pin outputs alarm interrupt to the cpu. this pin functions as an nch open drain output even when the ce pin is held at the low level. tmout pin outputs timer counter output pulses for watch-dog-timer and free-run- timer. this pin functions as an nch open drain output even when the ce pin is held at the low level. timer function is disabled and tmout is off state when the rs5c317 is in the oscillation halt sensing state. these pins configure an oscillator circuit by connecting a 32.768khz crystal oscilla - tor between the oscin and oscout pins and by connecting a capacitor between the oscin and vss pins. (any other oscillator circuit components are built into the RS5C317A/b.) 32khz clock output pin for peripheral circuit. the 32khz clock output is controlled by clkc pin and 32khz control register. the 32kout pin outputs 32khz clock when the clkc pin is held at high and clen=0, and this pin is held at high impedance state when the clkc pin and clen is in any other states and even when the clkc pin is open. cmos output. control pin for an output of the 32kout pin. this pin incorporates a pull-down- resistor. v dd and v ss is connected to power supply and ground respectively. ordinarily connected to v ss pin.
RS5C317A/b 4 absolute maximum ra tings recommended opera ting conditions absolute maximum ratings (v ss =0v) symbol item conditions ratings unit v dd supply voltage ?.3 to +7.0 v v i input voltage ?.3 to v dd +0.3 v v o1 output voltage 1 sio, 32kout ?.3 to v dd +0.3 v v o2 output voltage 2 intr, alrm, tmout ?.3 to +12 v p d power dissipation topt=25 c 300 mw topt operating temperature ?0 to +85 ?c tstg storage temperature ?5 to +125 ?c (v ss =0v, topt=?0 to +85?c) symbol item conditions min. typ. max. unit v dd supply voltage 2.5 6.0 v v clk time keeping voltage 1.6 6.0 v f xt oscillation frequency 32.768 khz c g external oscillation capacitance c l value of crystal=6 to 8pf 5 10 24 pf v pup pull-up voltage intr, alrm, tmout 10 v absolute maximum ratings are threshold limit values that must not be exceeded even for an instant under any conditions. moreover, such values for any two items must not be reached simultaneously. operation above these absolute maximum ratings may cause degradation or permanent damage to the device. these are stress ratings only and do not necessarily imply functional operation below these limits.
RS5C317A/b 5 dc chara cteristics unless otherwise specified: v ss =0v, v dd =3v, topt=?0 to +85?c, oscillation frequency=32.768khz,(c l =6pf, r 1 =30k ), c g =10pf a c chara cteristics (v ss =0v, topt=?0 to +85?c, c l =50pf) symbol item v dd 3 4.5v v dd 3 4.0v v dd 3 2.5v unit min. max. min. max. min. max. t ces ce set-up time 175 200 400 ns t ceh ce hold time 175 200 400 ns t cr ce inactive time 350 400 800 ns t sck sclk clock cycle time 350 400 800 ns t ckh sclk high time 175 200 400 ns t ckl sclk low time 175 200 400 ns t cks sclk to ce set-up time 60 80 120 ns t re data output start time (from rising 120 135 300 ns of sclk) (from falling of sclk) t rr data output delay time (from rising 120 135 300 ns of sclk) (from falling of sclk) t rz output floating time 120 135 300 ns t ds input data set-up time 50 60 120 ns t dh input data hold time 50 50 80 ns symbol item pin name conditions min. typ. max. unit v ih ??input voltage ce, sclk/sclk, 0.8v dd v dd v sio, clkc v il ??input voltage ce, sclk/sclk, 0 0.2v dd v sio, clkc i oh ??output current sio, 32kout v oh =v dd ?.5v ?.5 ma i ol1 ??output current sio, 32kout v ol1 =0.5v 0.5 ma i ol2 intr, alarm, tmout v ol2 =0.4v 1 r dn pull-down resistance ce 45 150 450 k i ih input current clkc v ih =3v 1 5 a i ilk input leakage current sclk/sclk v i =v dd or v ss ? 1 a i oz1 output leakage current sio, 32kout v o =v dd or v ss ? 2 a i oz2 intr, alarm, tmout v o =10v ? 5 i dd1 standby current 1 v dd v dd =3v 0.6 1.5 a input/output: open i dd2 standby current 2 v dd v dd =6v 0.8 2.0 a input/output: open c d internal oscillation cap. oscout 10 pf
RS5C317A/b 6 t s c k t c e s t c k s t c e h t c r t r e t r z t c k h t c k l t r r r e a d d a t a w r i t e d a t a t d s t d h c e s c l k s i o r e a d c y c l e w r i t e c y c l e s i o t s c k t c e s t c k s t c e h t c r t r e t r z t c k h t c k l t r r r e a d d a t a w r i t e d a t a t d s t d h c e s c l k s i o r e a d c y c l e w r i t e c y c l e s i o input/output conditions: v ih =0. 8 v dd , v il =0. 2 v dd , v oh =0. 8 v dd , v ol =0. 2 v dd ?RS5C317A ?rs5c317b timing char t s * ) any sclk/sclk state is allowed in the hatched area.
RS5C317A/b 7 functional description s 1. ad dressing * 1) all the listed data can be read and written. * 2) the ?mark indicates data which can be read only and set to ??when read. * 3) the adj/bsy bit of the control register is set to adj for write operation and bsy for read operation. * 4) the wten/xstp bit of the control register is set to wten for write operation and xstp for read operation. * 5) the clock/calendar counter and the alarm register can be selected when the bank=0 and bank=1 respectively. to designate the ba nk is unnec - essary for interrupt cycle register and control register 1/2. * 6) the wten bit and test bit are set to ??when ce is ?ow? * 7) when the crystal oscillator is stopped after initial power-on or supply voltage drop, xstp=1, the timer register and clen bit o f the 32khz control reg - ister perform as follows: clen=0 tm3=tm2=tm1=tmcl=0 (timer halts) * 8) the clen data can be read only and set to 0 when clkc is ?? address registers data * 1 a3 a2 a1 a0 d3 d2 d1 d0 0 0 0 0 0 1-second counter (bank=0) s 8 s 4 s 2 s 1 day-of-the-week alarm register 1 (bank=1) aw 3 aw 2 aw 1 aw 0 1 0 0 0 1 10-second counter (bank=0) ? 2 s 40 s 20 s 10 day-of-the-week alarm register 2 (bank=1) alc aw 6 aw 5 aw 4 2 0 0 1 0 1-minute counter (bank=0) m 8 m 4 m 2 m 1 1-minute alarm register (bank=1) am 8 am 4 am 2 am 1 3 0 0 1 1 10-minute counter (bank=0) m 40 m 20 m 10 10-minute alarm register (bank=1) am 40 am 20 am 10 4 0 1 0 0 1-hour counter (bank=0) h 8 h 4 h 2 h 1 1-hour alarm register (bank=1) ah 8 ah 4 ah 2 ah 1 5 0 1 0 1 10-hour counter (bank=0) p/a, h 20 h 10 10-hour alarm register (bank=1) ale ap/a, ah 20 ah 10 6 0 1 1 0 day-of-the-week counter (bank=0) w 4 w 2 w 1 7 0 1 1 1 interrupt cycle register (bank=0, 1) ct 3 ct 2 ct 1 ct 0 8 1 0 0 0 1-day counter (bank=0) d 8 d 4 d 2 d 1 9 1 0 0 1 10-day counter (bank=0) d 20 d 10 timer register * 7 (bank=1) tm 3 tm 2 tm 1 tmcl a 1 0 1 0 1-month counter (bank=0) mo 8 mo 4 mo 2 mo 1 32khz control register * 7 (bank=1) clen * 8 b 1 0 1 1 10-month counter (bank=0) mo 10 c 1 1 0 0 1-year counter (bank=0) y 8 y 4 y 2 y 1 d 1 1 0 1 10-year counter (bank=0) y 80 y 40 y 20 y 10 e 1 1 1 0 control register 1 (bank=0, 1) ctfg alfg wte n * 6 /xst p * 4 adj/bsy* 3 f 1 1 1 1 control register 2 (bank=0, 1) 12/24 tmr bank * 5 test * 6
RS5C317A/b 8 2. register s 2.1 contr ol register 1 (at eh) d 3 d 2 d 1 d 0 c t f g a l f g x s t p b s y c t f g a l f g w t e n a d j ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) 3 0 - s e c o n d a d j u s t m e n t b i t a d j d e s c r i p t i o n 0 1 o r d i n a r y o p e r a t i o n s e c o n d d i g i t a d j u s t m e n t b s y d e s c r i p t i o n 0 1 o r d i n a r y o p e r a t i o n s e c o n d d i g i t c a r r y o r a d j u s t m e n t c l o c k / c o u n t e r b u s y - s t a t e i n d i c a t i o n b i t w t e n d e s c r i p t i o n 0 1 d i s a b l i n g o f 1 - s e c o n d d i g i t c a r r y f o r c l o c k c o u n t e r e n a b l i n g o f 1 - s e c o n d d i g i t c a r r y f o r c l o c k c o u n t e r c l o c k c o u n t e r e n a b l e / d i s a b l e s e t t i n g b i t x s t p d e s c r i p t i o n 0 1 o r d i n a r y o s c i l l a t i o n o s c i l l a t o r h a l t s e n s i n g o s c i l l a t o r h a l t s e n s i n g b i t a l f g d e s c r i p t i o n 0 1 u n m a t c h e d a l a r m r e g i s t e r w i t h c l o c k c o u n t e r m a t c h e d a l a r m r e g i s t e r w i t h c l o c k c o u n t e r a l a r m f l a g b i t c t f g d e s c r i p t i o n 0 1 i n t r = o f f e n a b l i n g o f w r i t e o p e r a t i o n w h e n c t 3 b i t i s s e t t o 1 i n t r = l e n a b l i n g o f w r i t e o p e r a t i o n w h e n c t 3 b i t i s s e t t o 1 i n t e r r u p t f l a g b i t 2.1-1 (adj) the following operations are performed by setting the adj bit to 1. after this bit is set to 1, the bsy bit is set to 1 for the maximum duration of 122.1 s. if the wten bit is 0, these adjustment operations are started after the wten bit is set to 1. 1) for second digits ranging from ?0?to ?9?seconds: time counters smaller than seconds are reset and second digits are set to ?0? 2) for second digits ranging from ?0?to ?9?seconds: time counters smaller than seconds are reset and second digits are set to ?0? minute digits are incremented by 1.
RS5C317A/b 9 2.1-2 (bsy) when the bsy bit is 1, the clock and calendar counter are being updated. consequently, write operation should be performed for the counters when the bsy bit is 0. meanwhile, read operation is normally performed for the counters when the bsy bit is 0, but can be performed without checking the bsy bit as long as appropriate software is provided for preventing read errors. (refer to 15. typical software-based operations.) the bsy bit is set to 1 in the following three cases: 2.1-3 (wten) the wten bit should be set to 0 to check that the bsy bit is 0 when performing read and write operations for the clock and calendar counters. for read operation, the wten bit may be left as 1 without checking the bsy bit as long as appropriate measures such as read repetition are provided for preventing read errors. the wten bit should be set to 1 after completing read and write operations, or will automatically be set to 1 by switching the ce pin to the low level. if 1-second digit carry occurs when the wten bit is 0, a second digit increment by 1 occurs when the wten bit is set to 1. there may be a possibility causing a time delay when it takes 1/1024 second or more to set wten bit from 0 to 1, read data in state of wten=1 in such a case. (refer to the item 15.3) 2.1-4 (xstp) the xstp bit senses the oscillator halt. when the ce pin is held at the low level, the xstp bit is set to 1 once the crystal oscillator is stopped after initial power-on or supply voltage drop and left to be 1 after it is restarted. when the ce pin is held at the high level, the xstp bit is left as it was when the ce pin was held at the low level without checking oscillation stop. as such, the xstp bit can be used to validate clock and calendar count data after power-on or supply voltage drop. the xstp bit is set to 0 when any data is written to the control register 1 (at eh) with ordinary oscillation. 2.1-5 (alfg) the alfg bit can be set to 1 when the ale bit set to 1 with alarm interruption (intr=l). m a x . 1 2 2 . 1 s s e t t i n g o f t h e a d j b i t t o 1 c o m p l e t i o n o f s e c o n d d i g i t a d j u s t m e n t ( i ) a d j u s t m e n t o f s e c o n d d i g i t s b y 3 0 s e c o n d s ( i i ) s e c o n d d i g i t s i n c r e m e n t b y 1 ( s u b j e c t t o 1 - s e c d i g i t c a r r y w h e n t h e w t e n b i t i s s w i t c h e d f r o m 0 t o 1 ) ( i i i ) o r d i n a r y 1 - s e c d i g i t c a r r y m a x . 9 1 . 6 s s e t t i n g o f t h e w t e n b i t t o 1 e n d o f s e c o n d d i g i t i n c r e m e n t b y 1 9 1 . 6 s e n d o f s e c o n d d i g i t c a r r y p u l s e m a t c h e d a l a r m r e g i s t e r m a t c h e d a l a r m r e g i s t e r a l f g i s w r i t t e n t o 0 m a t c h e d a l a r m r e g i s t e r a l f g i n t r
RS5C317A/b 10 2.1-6 (ctfg) the ctfg bit is set to 1 when interrupt pulses are output from the intr pin held at the low level. there are two interrupt modes selectable: the pulse mode (when the ct 3 bit is set to 0) and the level mode (when the ct 3 bit is set to 1). the ctfg bit can be set only when the ct 3 is set to 1. setting the ctfg bit to 1 switches the intr pin to the low level while setting the ctfg bit to 0 turns off the intr pin. * 1) the symbol * ?in the above table indicates 0 or 1. 0 . 9 7 7 m s i n t e r r u p t ( s e c o n d c o u n t - u p ) i n t e r r u p t ( s e c o n d c o u n t - u p ) s e t t i n g c t f g b i t t o 0 c t f g i n t r c t f g i n t r 0 . 5 s 0 . 4 8 8 m s c t f g i n t r * 2) * 3) * 4) interrupt cycle register intr output description ct 3 ct 2 ct 1 ct 0 0 * * 1 0 0 off interrupt halt 0 * 0 1 on fixing the intr pin at low level 0 * 1 0 0.977ms cycle: 0.977ms (1/1024hz) duty 50% * 2 0 * 1 1 0.5s cycle: 0.5s (1/2hz) * 3 1 0 0 0 1s every second * 4 1 0 0 1 10s every 10 seconds * 4 (for display of second digits: 00, 10, 20, 30, 40 and 50) 1 0 1 0 1 minute every minute (00 second) * 4 1 0 1 1 10 minutes every 10 minutes (00 second) * 4 (for display of minute digits: 00, 10, 20, 30, 40 and 50) 1 1 0 0 1 hour every hour (00 minute and 00 second) * 4 1 1 0 1 1 day every day (0 hour, 00 minute and 00 second a.m.) * 4 1 1 1 0 1 week every week * 4 (0 week, 0 hour, 00 minute and 00 second a.m.) 1 1 1 1 1 month every month * 4 (1 day, 0 hour, 00 minute and 00 second a.m.)
RS5C317A/b 11 2.2 contr ol register 2 (at fh) d 3 d 2 d 1 d 0 1 2 / 2 4 t m r b a n k t e s t 1 2 / 2 4 t m r b a n k t e s t ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) b i t f o r t e s t i n g * 1 t e s t d e s c r i p t i o n 0 1 t e s t i n g m o d e o r d i n a r y o p e r a t i o n m o d e b a n k d e s c r i p t i o n 0 1 c l o c k / c a l e n d a r c o u n t e r a l a r m r e g i s t e r b a n k s e l e c t i o n b i t * 2 t m r d e s c r i p t i o n 0 1 c o n t i n u o s t i m e r o p e r a t i o n r e s u m e t i m e r o p e r a t i o n a f t e r r e s e t r e s e t b i t f o r t i m e r c o u n t e r * 3 1 2 / 2 4 d e s c r i p t i o n 0 1 1 2 - h o u r t i m e d i s p l a y s y s t e m ( s e p a r a t e f o r m o r n i n g s a n d a f t e r n o o n s ) 2 4 - h o u r t i m e d i s p l a y s y s t e m 1 2 / 2 4 - h o u r t i m e d i s p l a y s y s t e m s e l e c t i o n b i t * 4 * 1) (test) set the test bit to 1 in ordinary operation. test bit is set automatically to 1 when the ce pin is ?? * 2) (bank) there is no need to designate bank bit for interrupt cycle register and control register 1/2. * 3) (tmr) the period for timer output is set in the ?imer register? * 4) (12/24) the 12/24 bit specifies time digit display in bcd code. either the 12-hour or 24-hour time display system should be selected before time setting. 24-hour time display system 12-hour time display system 24-hour time display system 12-hour time display system 00 12 (am12) 12 32 (pm12) 01 01 (am 1) 13 21 (pm 1) 02 02 (am 2) 14 22 (pm 2) 03 03 (am 3) 15 23 (pm 3) 04 04 (am 4) 16 24 (pm 4) 05 05 (am 5) 17 25 (pm 5) 06 06 (am 6) 18 26 (pm 6) 07 07 (am 7) 19 27 (pm 7) 08 08 (am 8) 20 28 (pm 8) 09 09 (am 9) 21 29 (pm 9) 10 10 (am10) 22 30 (pm10) 11 11 (am11) 23 31 (pm11)
RS5C317A/b 12 2.3 interrupt c yc le register (at 7h) d3 d2 d1 d0 aw 3 aw 2 aw 1 aw 0 (for read/write) day-of-the-week 1 (a t 0h) alc aw 6 aw 5 aw 4 (for read/write) day-of-the-week 2 (a t 1h) am 8 am 4 am 2 am 1 (for read/write) 1-minute time digit (a t 2h) * am 40 am 20 am 10 (for read/write) 10-minute time digit (a t 3h) ah 8 ah 4 ah 2 ah 1 (for read/write) 1-hour time digit (a t 4h) ale * ap/a, ah 20 ah 10 (for read/write) 10-hour time digit (a t 5h) 2.4 alarm register s f or da y-of-the-week, 1-min ute , 10-min ute , 1-hour , 10-hour (b ank1, at 0h-5h) * 1) (ct 3 to ct 0 ) the ct 3 to ct 0 bits are used to select the interrupt cycle and output mode at the intr pin. there are two interrupt modes selectable: the pul se mode (when the ct 3 bit is set to 0) and the level mode (when the ct 3 bit is set to 1). the interrupt cycle and output mode at the intr pin are shown in detail in the section on the ctfg bit in ?.1 control register 1 (at eh)? * 1) the * ?mark in the above table indicates data which are set to 0 for read cycle and not set for write cycle. * 2) 10-hour time digit indicates ap/a and ah 20 with 12-hour and 24-hour time system respectively. * 3) make sure set an actual time-data to the alarm registers when the alarm function is activated as any imaginary alarm-data will never be match with the actual time. * 4) the intr pin can output matched alarm interruption when the alc bit is set 0 and halt output when the alc bit is set to 1. * 5) the alarm function is disabled when the ale bit is set 0 and is enables when the ale bit is set 1. * 6) examples of setting alarm time * 7) hour digits show ?2?and ?2?when the time is am 00:00 and pm 00:00 respectively in the 12-hour system. * 8) no alarm interruption is output when all the bit from aw 0 through aw 6 is set to 0. * 9) each of the aw 0 through aw 6 corresponds to the day-of-the-week counter such as (w 4 , w 2 , w 1 )=(0, 0, 0) through (1, 1, 0). designation of day-of- the-week and aw 0 through aw 6 in the above table is one example. d 3 d 2 d 1 d 0 c t 3 c t 2 c t 1 c t 0 c t 3 c t 2 c t 1 c t 0 ( f o r w r i t e o p e r a t i o n ) ( f o r r e a d o p e r a t i o n ) b i t s f o r s e l e c t i n g t h e i n t e r r u p t c y c l e a n d o u t p u t m o d e a t t h e i n t r p i n * 1 day-of-the-week 12-hour system 12-hour system setting alarm time sun. mon. tue. wed. thu. fri. sat. 10- 1- 10- 1- 10- 1- 10- 1- aw0 aw1 aw2 aw3 aw4 aw5 aw6 hour hour min min hour hour min min am 00:00 every day 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 am 01:30 every day 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 am 1 1 : 59 every day 1 1 1 1 1 1 1 1 1 5 9 1 1 5 9 pm 00:00 0 1 1 1 1 1 0 3 2 0 0 1 2 0 0 on monday through friday pm 01:30 on sunday 1 0 0 0 0 0 0 2 1 3 0 1 3 3 0 pm 11:59 on monday, 0 1 0 1 0 1 0 3 1 5 9 2 3 5 9 wednesday, and friday
RS5C317A/b 13 2.5 timer register (b ank 1, at 9h) cycle time setting table for the time counter (the * ?mark indicates 0 or 1.) d 3 d 2 d 1 d 0 t m 3 t m 2 t m 1 t m c l ( f o r r e a d / w r i t e ) c l o c k f r e q u e n c y s e l e c t i o n b i t f o r t h e t i m e r c o u n t e r * 1 p e r i o d s e l e c t i o n b i t f o r t h e t i m e r c o u n t e r * 2 t m c l d e s c r i p t i o n 0 1 c l o c k f r e q u e n c y = 5 1 2 h z ( 1 . 9 5 3 m s ) c l o c k f r e q u e n c y = 1 6 h z ( 6 2 . 5 m s ) tm 3 tm 2 tm 1 tmcl t1 ( cycle time for t2 (time between setting t3 ( cycle time for watch-dog-timer) * 3 tmr=1 and tmout output) * 4 free-run timer) * 5 0 0 0 * timer halts timer halts timer halts 0 0 1 0 1.953ms 1.953 to 3.907ms 3.906ms 0 1 0 0 5.859ms 5.859 to 7.813ms 7.812ms 0 1 1 0 9.765ms 9.765 to 11.72ms 11.719ms 1 0 0 0 13.67ms 13.67 to 15.63ms 15.625ms 1 0 1 0 17.57ms 17.57 to 19.54ms 19.531ms 1 1 0 0 21.48ms 21.48 to 23.44ms 23.437ms 1 1 1 0 25.39ms 25.39 to 27.35ms 27.344ms 0 0 1 1 62.5ms 62.5 to 125ms 125ms 0 1 0 1 187.5ms 187.5 to 250ms 250ms 0 1 1 1 312.5ms 312.5 to 375ms 375ms 1 0 0 1 437.5ms 437.5 to 500ms 500ms 1 0 1 1 562.5ms 562.5 to 625ms 625ms 1 1 0 1 687.5ms 687.5 to 750ms 750ms 1 1 1 1 812.5ms 812.5 to 875ms 875ms * 1) (tmcl) ?12hz?and ?6hz?are selectively available. when the ?stp?bit is set to 1, the ?mcl?bit is automatically set to 0. ther e may be possibility to be ahead or behind of the clock counter at maximum of a halt of clock frequency (512hz or 16hz), when the ?dj?bit is set to 1 in the control register-1. * 2) (tm 3 -tm 1 ) when the ?stp?bit is set to 1 the ?m 3 , tm 2 ? and ?m 1 ?is automatically set to 0, the timer counter halts. * 3) t1: the maximum disable time for timer output, tmout=l, after setting the ?mr?bit to 1. * 4) t2: time between timer output and setting the ?mr?bit to 1, or setting the timer register to any value. * 5) t3: timer output cycle time without setting ?mr?bit to 1, cycle time for free-run-timer.
RS5C317A/b 14 clkc pin clen bit 32kout output l (open) 0 (prohibited to write) high impedance h 0 32khz clock output h 1 high impedance d3 d2 d1 d0 s 8 s 4 s 2 s 1 (for read/write) 1-second time digit (a t 0h) * s 40 s 20 s 10 (for read/write) 10-second time digit (a t 1h) m 8 m 4 m 2 m 1 (for read/write) 1-minute time digit (a t 2h) * m 40 m 20 m 10 (for read/write) 10-minute time digit (a t 3h) h 8 h 4 h 2 h 1 (for read/write) 1-hour time digit (a t 4h) * * p/a or h 20 h 10 (for read/write) 10-hour time digit (a t 5h) * 6) timing diagram for tmout * 7) writing operation to the timer register makes the timer counter to start operation with resetting. t m r ? 1 t m r ? 1 0 . 9 7 7 m s m a x . t 1 t 2 t 3 t m o u t d3 d2 d1 d0 * * * clen (for read/write) * 1) the * ?mark indicates data which are set to 0 for read cycle and not set for write cycle. * 2) (clen) control bit for 32khz output the clen bit is set to 0 when the xstp=1. clen is not writable and set to 0 when clkc pin level low/open. * 3) 32kout condition 2.6 32khz contr ol register (b ank 1, at ah) 3. counter s 3.1 cloc k counter (b ank 0, at 0h-5h) * 1) the * ?mark indicates data which are set to 0 for read cycle and not set for write cycle. * 2) any carry to 1-second digits from the second counter is disabled when the wten bit (of the control register 1) is set to 0. * 3) time digit display (bcd code): second digits : range from 00 to 59 and carried to minute digits when incremented from 59 to 00. minute digits : range from 00 to 59 and carried to hour digits when incremented from 59 to 00. hour digits : range as shown in the section on the 12/24 bit and carried to day and day-of-the-week digits when incremented from 11 p.m. to 1 2 a.m. or 23 to 00. * 4) any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from low er-order ones cause the clock counter to malfunction.
RS5C317A/b 15 d3 d2 d1 d0 d 8 d 4 d 2 d 1 (for read/write) 1-day calendar digit (a t 8h) * * d 20 d 10 (for read/write) 10-day calendar digit (a t 9h) mo 8 mo 4 mo 2 mo 1 (for read/write) 1-month calendar digit (a t ah) * * * mo 10 (for read/write) 10-month calendar digit (a t bh) y 8 y 4 y 2 y 1 (for read/write) 1-year calendar digit (a t ch) y 80 y 40 y 20 y 10 (for read/write) 10-year calendar digit (a t dh) d3 d2 d1 d0 * w 4 w 2 w 1 (for read/write) day-of-the-week counter * 1) the * ?mark indicates data which are set to 0 for read cycle and not set for write cycle. * 2) day-of-the-week digits are incremented by 1 when carried to 1-day digits. * 3) day-of-the-week digits display (incremented in septimal notation): (w 4 , w 2 , w 1 )=(000) ? (001) ? ? ? (110) ? (000) the relation between days of the week and day-of-the-week digits is user changeable (e.g. sunday=000). * 4) the (w 4 , w 2 , w 1 ) should not be set to (111). 3.2 da y-of-the-week counter (b ank 0, at 6h) 3.3 calendar counter (b ank 0, at 8h-dh) * 1) the * ?mark indicates data which are set to 0 for read cycle and not set for write cycle. * 2) the automatic calendar function provides the following calendar digit displays in bcd code. day digits : range from 1 to 31 (for january, march, may, july, august, october, and december). range from 1 to 30 (for april, june, september, and november). range from 1 to 29 (for february in leap years). range from 1 to 28 (for february in ordinary years). carried to month digits when cycled to 1. month digits : range from 1 to 12 and carried to year digits when cycled to 1. year digits : range from 00 to 99 and counted as 00, 04, 08, ..., 92, and 96 in leap years. * 3) any registered imaginary time should be replaced with actual time as carrying to such registered imaginary time digits from low er-order ones cause the clock counter to malfunction.
RS5C317A/b 16 usa ges 1. read data (for the RS5C317A) the real-time clock becomes accessible by switching the ce pin from the low level to high level to enable inter - facing with the cpu and then inputting setting data (control bits and address bits) to the sio pin in synchronization with shift clock pulses from the sclk pin. the input data are registered in synchronization with the falling edge of the sclk. when the data is read, the read cycle shall be set by control bits then registered data can be read out from sio pin in synchronization with the rising edge of the sclk. ?control bits r/w: establishes the read mode when set to 1, and the write mode when set to 0. ad: writes succeeding addressing bits (a3-a0) to the address register when set to 1 with the dt bit set to 0 and performs no such write operation in any other case. dt: writes data bits to counter or register specified by the address register set just before when set to 1 with the r/w and ad bits set equally to 0 and performs no such write oper - ation in any other case. ?address bits a3-a0: inputs the bits msb to lsb in the address table describing the functions. 1.1 read cyc le flo w 1. the ce pin is switched from ??to ?? 2. four control bits (with the first bit ignored) and four read address bits are input from the sio pin. at this time, control bits r/w and ad are set equally to 1 while a control bit dt is set to 0. (see the sclk 1a-8a) 3. the sio pin enters the output mode at the rising edge of the shift clock pulse 2b from the sclk pin while the four read bits (msb ? lsb) at designated addresses are output at the rising edge of the shift clock pulse 5b. (see the figure below) 4. then, the sio pin returns to the input mode at the rising edge of the shift clock pulse 1c. afterwards control bits and address bits are input at the shift clock pulses 1c in the same manner as at the shift clock pulse 1a. 5. at the end of read cycle, the ce pin is switched from ??to ??(after t ceh from the falling edge of the eighth shift clock pulse from the sclk pin). following on read cycle, write operation can be performed by setting con - trol bits in the write mode at the shift clock pulse 1c and later with the ce pin held at ?? 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 c 2 c 3 c r / w a d d t a 3 a 2 a 1 a 0 d 3 d 2 d 1 d 0 r / w a d * * c e s c l k i n p u t t o s i o p i n o u t p u t f r o m s i o p i n w r i t i n g t o s h i f t r e g i s t e r w r i t i n g t o a d d r e s s r e g i s t e r s e t t i n g o f c o n t r o l b i t s c o n t r o l b i t s ( h i - z ) ( h i - z ) ( h i - z ) r e a d d a t a s e t t i n g o f s i o p i n i n o u t p u t m o d e s h i f t i n g d a t a s e t t i n g o f s i o p i n i n i n p u t m o d e ( i n t e r n a l p r o c e s s i n g ) a d d r e s s b i t s * ) in the above figure, the * ?mark indicates arbitrary data; the ?mark indicates unknown data. the ? ?mark indicates data which are available when the sio pin is held at ?? ?? or hiz level. the diagonally shaded area of the ce and the sclk pins indicate ??or ??
RS5C317A/b 17 2. write data (for the RS5C317A) writing data to the real-time clock requires inputting setting data (control bits, address bits and data bits) to the sio pin and then establishing the write mode by using a control bit r/w in the same manner as in read operation. ?data bits d3-d0: inputs the data bits msb to lsb in the addressing table describing the functions. 2.1 write cyc le flo w 1. the ce pin is switched from ??to ?? 2. four control bits (with the first bit ignored) and four write address bits are input from the sio pin. at this time, control bits r/w and dt are set equally to 0 while a control bit ad is set to 1. (see the sclk 1a-8a) 3. four control bits and four bits of data to be written are input in the descending order of their significance. at this time, control bits r/w and ad are set equally to 0 while a control bit dt is set to 1. (see the clock 1b-8b) 4. when write cycle is continued, control bits and address bits are input at the shift clock pulse 1c and later in the same manner as at the shift clock pulse 1a. 5. at the end of write operation, control bits r/w, ad, and dt are set equally to 0 (at the falling edge of shift clock pulse 5a and later from the sclk pin) or the ce pin is switched from ??to ??(after t ceh from the falling edge of the eighth shift clock pulse from the sclk pin). following on write cycle, read operation can be performed by setting control bits in the read mode at the shift clock pulse 1c and later with the ce pin held at ?? 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 c 2 c 3 c r / w a d d t a 3 a 2 a 1 a 0 r / w a d d t d 3 d 2 d 1 d 0 r / w a d * * * * c e ( i n t e r n a l p r o c e s s i n g ) s c l k i n p u t t o s i o p i n o u t p u t f r o m s i o p i n w r i t i n g t o s h i f t r e g i s t e r w r i t i n g t o a d d r e s s r e g i s t e r s e t t i n g o f c o n t r o l b i t s e n d o f w r i t e o p e r a t i o n s e t t i n g o f c o n t r o l b i t s c o n t r o l b i t s a d d r e s s b i t s c o n t r o l b i t s d a t a b i t s ( h i z ) ( h i z ) * ) in the above figure, the * ?mark indicates arbitrary data; and the diagonally shaded area of ce and sclk indicates ??or ?? * ) control bits and address bits are described in the previous section on read cycle.
RS5C317A/b 18 3. read data (for the rs5c317b) the real-time clock becomes accessible by switching the ce pin from the low level to high level to enable inter - facing with the cpu and then inputting setting data (control bits and address bits) to the sio pin in synchronization with shift clock pulses from the sclk pin. the input data are registered in synchronization with the rising edge of the sclk. when the data is read, the read cycle shall be set by control bits then registered data can be read out from sio pin in synchronization with the falling edge of the sclk. ?control bits r/w: establishes the read mode when set to 1, and the write mode when set to 0. ad: writes succeeding addressing bits (a3-a0) to the address register when set to 1 with the dt bit set to 0 and performs no such write operation in any other case. dt: writes data bits to counter or register specified by the address register set just before when set to 1 with the r/w and ad bits set equally to 0 and performs no such write oper - ation in any other case. ?address bits a3-a0: inputs the bits msb to lsb in the address table describing the functions. 3.1 read cyc le flo w 1. the ce pin is switched from ??to ?? 2. four control bits (with the first bit ignored) and four read address bits are input from the sio pin. at this time, control bits r/w and ad are set equally to 1 while a control bit dt is set to 0. (see the sclk 1a-8a) 3. the sio pin enters the output mode at the falling edge of the shift clock pulse 2b from the sclk pin while the four read bits (msb ? lsb) at designated addresses are output at the falling edge of the shift clock pulse 5b. (see the figure below) 4. then, the sio pin returns to the input mode at the falling edge of the shift clock pulse 1c. afterwards control bits and address bits are input at the shift clock pulses 1c in the same manner as at the shift clock pulse 1a. 5. at the end of read cycle, the ce pin is switched from ??to ??(after t ceh from the rising edge of the eighth shift clock pulse from the sclk pin). following on read cycle, write operation can be performed by setting con - trol bits in the write mode at the shift clock pulse 1c and later with the ce pin held at ?? 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 c 2 c 3 c r / w a d d t a 3 a 2 a 1 a 0 d 3 d 2 d 1 d 0 r / w a d * * c e s c l k i n p u t t o s i o p i n o u t p u t f r o m s i o p i n w r i t i n g t o s h i f t r e g i s t e r w r i t i n g t o a d d r e s s r e g i s t e r s e t t i n g o f c o n t r o l b i t s c o n t r o l b i t s a d d r e s s b i t s ( h i - z ) ( h i - z ) ( h i - z ) r e a d d a t a ( i n t e r n a l p r o c e s s i n g ) s h i f t i n g d a t a s e t t i n g o f s i o p i n i n i n p u t m o d e s e t t i n g o f s i o p i n i n o u t p u t m o d e * ) in the above figure, the * ?mark indicates arbitrary data; the ?mark indicates unknown data. the ? ?mark indicates data which are available when the sio pin is held at ?? ?? or hiz level. the diagonally shaded area of the ce and the sclk pins indicate ??or ??
RS5C317A/b 19 4. write data (for the rs5c317b) writing data to the real-time clock requires inputting setting data (control bits, address bits and data bits) to the sio pin and then establishing the write mode by using a control bit r/w in the same manner as in read operation. ?data bits d3-d0: inputs the data bits msb to lsb in the addressing table describing the functions 4.1 write cyc le flo w 1. the ce pin is switched from ??to ?? 2. four control bits (with the first bit ignored) and four write address bits are input from the sio pin. at this time, control bits r/w and dt are set equally to 0 while a control bit ad is set to 1. (see the sclk 1a-8a) 3. four control bits and four bits of data to be written are input in the descending order of their significance. at this time, control bits r/w and ad are set equally to 0 while a control bit dt is set to 1. (see the sclk 1b-8b) 4. when write cycle is continued, control bits and address bits are input at the shift clock pulse 1c and later in the same manner as at the shift clock pulse 1a. 5. at the end of write operation, control bits r/w, ad, and dt are set equally to 0 (at the rising edge of shift clock pulse 5a and later from the sclk pin) or the ce pin is switched from ??to ??(after t ceh from the rising edge of the eighth shift clock pulse from the sclk pin). following on write cycle, read operation can be performed by setting control bits in the read mode at the shift clock pulse 1c and later with the ce pin held at ?? r / w a d d t a 3 a 2 a 1 a 0 r / w a d d t d 3 d 2 d 1 d 0 r / w a d * * * * c e ( i n t e r n a l p r o c e s s ) s c l k i n p u t t o s i o p i n o u t p u t f r o m s i o p i n w r i t i n g t o s h i f t r e g i s t e r w r i t i n g t o a d d r e s s r e g i s t e r s e t t i n g o f c o n t r o l b i t s e n d o f w r i t e o p e r a t i o n s e t t i n g o f c o n t r o l b i t s c o n t r o l b i t s a d d r e s s b i t s c o n t r o l b i t s d a t a b i t s ( h i z ) ( h i z ) 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 a 1 b 2 b 3 b 4 b 5 b 6 b 7 b 8 b 1 c 2 c 3 c * ) in the above figure, the * ?mark indicates arbitrary data; and the diagonally shaded area of ce and sclk indicates ??or ?? * ) control bits and address bits are described in the previous section on read cycle.
RS5C317A/b 20 considerations 5. ce pin 1) switching the ce pin to the high level enables the sclk/sclk and sio pins, allowing data to be serially read from and written to the sio pin in synchronization with shift clock pulses input from the sclk/sclk pin. 2) switching the ce pin to the low level or opening disables the sclk/sclk and sio pins, causing high imped - ance and resetting the internal interfacing circuits such as the shift register. while data of the address register and bank bit which have been written just before should be preserved. 3) the ce pin should be held at the low level or open state when no access is made to the rs5c317. the ce pin incorporates a pull-down resistor. 4) during system power-down (being back-up battery powered), the low-level input of the ce pin should be brought as close as possible to the vss level to minimize the loss of charge in the battery. 5) holding the ce pin at the high level for more than 2.5 seconds mainly forces 1hz interrupt pulses to be output from the intr pin for oscillation frequency measurement. when the ce pin is held at the high level for less than 1.5 seconds, no pulse is output. 6) the ce pin should be held at the low level in order to enable oscillator halt sensing. holding the ce pin at the high level, therefore, disables oscillator halt sensing, retaining the value of the xstp (oscillator halt sensing) bit which exists immediately before the ce pin is switched to the high level. * ) RS5C317A: sclk rs5c317b: sclk when the power turns on from 0v, the ce pin should be set low or open once. s c l k / s c l k * s i o c e s h i f t c l o c k p u l s e s a d d r e s s d a t a w r i t e d a t a r e a d d a t a r e a d c o n t r o l b i t c o n t r o l b i t
RS5C317A/b 21 6. configuration of oscillating cir cuit r f r d c d o s c i n o s c o u t 3 2 k h z v d d v d d c g v s s a typical external device: x'tal : 32.768khz (r 1 =30k typ.) (c l =6pf to 8pf) c g =8pf to 20pf typical values of internal devices r f =15m (typ.) r d =60k (typ.) c d =10pf (typ.) considerations in mounting components surrounding oscillating circuit other relevant considerations 1) mount the crystal oscillators and c g in the closest possible position to the ic. 2) avoid laying any signal or power line close to the oscillation circuit (particularly in the area marked with ? a ? ?in the above figure). 3) apply the highest possible insulation resistance between the oscin or oscout pin and the pcb. 4) avoid using any long parallel line to wire the oscin or oscout pin. 5) take extreme care not to cause condensation, which leads to various problems such as oscillation halt. 1) when applying an external input of clock pulses (32.768khz) to the oscin pin: dc coupling ............ prohibited due to mismatching input levels. ac coupling ............. permissible except that unpredictable results may occur in oscillator halt sensing due to possible sensing errors caused by noises, etc. 2) avoid using the oscillator output of the rs5c317 (from the oscout pin) to drive any other ic for the pur - pose of ensuring stable oscillation. * ) the oscillation circuit is driven at a constant voltage of about 1.5v relative to the vss level. consequently, it generates a wave form having a peak-to-peak amplitude of about 1.5v on the positive side of the vss level.
RS5C317A/b 22 considerations in use of xstp bit 7. oscillator halt sensing oscillation halt can be sensed through monitoring the xstp bit with preceding setting of the xstp bit to 0 by writing any data to the control register 1. upon oscillator halt sensing, the xstp bit is switched from 0 to 1. this function can be applied to judge clock data validity. when the xstp bit is set to 1, the timer register bits and clen bit perform as follows: clen=0 tm 3 =tm 2 =tm 1 =tmcl=0 (timer halts) * 1) while the ce pin is held at the low level, the xstp bit is set to 1 upon power-on from 0v. note that any instantaneous power disconnection may cause operational failure. when the ce pin is held at the high level, osci llation halt is not sensed and the value of the xstp bit when the ce pin is held at the low level is retained. * 2) once oscillation halt has been sensed, the xstp bit is held at 1 even if oscillation is restarted. ensure error-free oscillation halt sensing by preventing the following: 1) instantaneous disconnection of vdd 2) condensation on the crystal oscillator 3) generation of noise on the pcb in the crystal oscillator 4) application of voltage exceeding prescribed maximum ratings to the individual pins of the ic p o w e r - o n f r o m 0 v * 1 x s t p o s c i l l a t i o n h a l t w r i t i n g o f d a t a t o c o n t r o l r e g i s t e r 1 ( i n t h e p r e s e n c e o f o s c i l l a t i o n ) o s c i l l a t i o n r e s t a r t * 2
RS5C317A/b 23 8. t ypical p o wer suppl y cir cuit 1) connect the capacitance of the oscillation circuit to the vss pin. 2) mount the high-and low-frequency by-pass capacitors in paral - lel and very close to the rs5c317. 3) connect the pull-up resistor of the intr pin to two different positions depending on whether the resistor is in use during battery back-up. when not in use during battery back-up ........... position a in the left figure when in use during battery back-up ........... position b in the left figure 4) timing of power-on, power-off and ce pin refer to following figure. 5) when a diode are in use in place of the components surround - ed by dotted lines, note that applying voltage to any input pins should be less than the rating of v dd +0.3v by using of schot - tky diode. o s c i n o s c o u t v d d r s 5 c 3 1 7 v s s b a s y s t e m s u p p l y v o l t a g e i n t r c 0 v v d d c e d 0 . 2 v d d m i n . 0 s m i n . 0 s m i n . 0 s c , d , e : m i n i m u m o p e r a t i n g v o l t a g e f o r c p u 0 . 2 v d d 0 . 2 v d d b a t t e r y v o l t a g e s y s t e m s u p p l y v o l t a g e e 9. oscillation frequenc y adjustment 9.1 oscillation frequenc y measurement 1) switch the ce pin to the high level and use a frequen - cy counter to measure a 1hz interrupt pulse output from the intr pin about 2.5 seconds later. 2) ensure that the frequency counter has more than six digits (on the order of 1 ppm). 3) place the c g between the oscin pin and the vss lev - el and pull up the intr pin output to the vdd. i n t r o s c o u t o s c i n v d d c e v s s 3 2 k h z + 5 v o r + 3 v f r e q u e n c y c o u n t e r c g
RS5C317A/b 24 any rise or fall in ambient temperature from its reference value ranging from 20 to 25 degrees celsius causes a time delay for a 32khz crystal oscillator. it is recommendable, therefore, to set slightly high oscillation fre - quency at room temperature. 9.2 oscillation frequenc y adjustment after adjustment, oscillation frequency is subject to fluctuations of an ambient temperature and supply voltage. see ?4. typical characteristic measurements? s e l e c t c r y s t a l o s c i l l a t o r n o o k o k n o f i x c g ( f o r f i x e d c a p a c i t a n c e ) ( f o r v a r i a b l e c a p a c i t a n c e ) c h a n g e c l v a l u e o f c r y s t a l o p t i m i z e c g e n d e n d f i x t h e c a p a c i t a n c e o f c g o p t i m i z e c e n t r a l v a r i a b l e c a p a c i t a n c e v a l u e m a k e f i n e f r e q u e n c y a d j u s t m e n t w i t h v a r i a b l e c a p a c i t a n c e . c h a n g e c l v a l u e o f c r y s t a l * 1 * 3 * 3 * 2 * 1) to ensure that the crystal is matched to the ic, inquire its crystal supplier about its c l (load capacitance) and r 1 (equivalent series resistance) values. it is recommended that the crystal should have the c l value range of 6 to 8pf and the typical r 1 value of 30k . * 2) to allow for the possible effects of floating capacitance, select the optimum capacitance of the c g on the mounted pcb. the standard and recom - mendable capacitance values of the c g range from 5 to 24pf and 8 to 20pf, respectively. when you need to change the frequency to get higher accuracy, change the c l value of the crystal. * 3) collate the central variable capacitance value of the c g with its oscillation frequency by adjusting the angle of rotation of the variable capacitance of the c g in such a manner that the actual variable capacitance value is slightly smaller than the central variable capacitance value. (i t is recommended that the central variable capacitance value should be slightly less than one half of the actual variable capacitance value beca use the smaller is vari - able capacitance, the greater are fluctuations in oscillation frequency.) in the case of an excessive deviation of the oscilla tion frequency from its required value, change the c l value of the crystal. note
RS5C317A/b 25 10. interrupt operation two interrupt operations are available: 1) alarm interrupt ........... when a registered time for alarm (such as day-of-the-week, hour or minute) coincide with calendar counter (such as day-of-the-week, hour or minute) interrupt to the cpu are requested with intr pin or alrm pin being ??(on). 2) periodic interrupt ...... the intr pin comes to a ??(on) state every registered period outputting interrupt request. function diagram of alarm and periodic interrupts are shown as follows: 10.1 alarm interrupt for setting an alarm time, designated time such as day-of the week, hour or minute should be set to the alarm registers being ale bit to 0. after that set the ale bit to 1, from this moment onward when such registered alarm time coincide with the value of calendar counter the alrm comes down to low (on). the alrm output can be controlled by operating to the ale and alfg bits. * 1) setting the alc into 1 halt output of the alarm interrupt from intr pin. * 2) both of alarm and periodic interrupt can operate regardless of the state of ce pin, ??or ?? * 1) the * ?mark indicates the time when the registered alarm day-of-the-week and time coincide with calendar counter. * 2) above figure describes in case of no periodic interruption. * 3) alfg indicates a reverse state of alrm output. a l c i n t r a l r m a l a r m i n t e r r u p t p e r i o d i c i n t e r r u p t a l a r m - c a l e n d a r c o i n c i d e n t p e r i o d ( 1 m i n . ) * * * * a l r m a l r m a l e ? 1 a l e ? 1 a l f g ? 0 a l e ? 0 a l e ? 0 a l e ? 1 m a x . 6 1 . 1 s
interrupt cycle register intr output description ct 3 ct 2 ct 1 ct 0 0 * * 1 0 0 off interrupt halt 0 * 0 1 on fixing the intr pin to the low level 0 * 1 0 0.977ms cycle: 0.977ms (1/1024hz) duty 50% 0 * 1 1 0.5s cycle: 0.5s (1/2hz) 1 0 0 0 1s every second 1 0 0 1 10s every 10 seconds (for display of second digits: 00, 10, 20, 30, 40 and 50) 1 0 1 0 1 min every minute (00 second) 1 0 1 1 10 min every 10 minutes (for display of minute digits: 00, 10, 20, 30, 40 and 50) 1 1 0 0 1 hour every hour (00 minute and 00 second) 1 1 0 1 1 day every day (0 hour, 00 minute and 00 second a.m.) 1 1 1 0 1 week every week (0 week, 0 hour, 00 minute and 00 second a.m.) 1 1 1 1 1 month every month (1st day, 0 hour, 00 minute and 00 second a.m.) RS5C317A/b 26 10.2 p eriodic (cloc k) interrupt the intr pin output, the interrupt cycle register, and the ctfg bit can be used to interrupt the cpu in a certain cycle. the interrupt cycle register can be used to select either one of two interrupt output modes: the pulse mode (when the ct 3 bit is set to 0) and the level mode (when the ct 3 bit is set to 1). 10.2-1 interr upt cycle selection 10.2-2 pulse mode interr upt when the ct 3 bit is set to 0 and provides four interrupt cycles, off, on, 1024hz, and 2hz can be selected. the ctfg bit cannot be set because it is used for output monitoring. 10.2-3 le v el mode interr upt when the ct 3 bit is set to 1, clock-interlocked cycles in increments of one second to one month can be selected. the ctfg bit can be written; writing 1 to the ctfg bit switches the intr pin to the low level while writing 0 to the ctfg bit turns off the intr pin. * 1) the * ?mark indicates 0 or 1. t 1 0 . 4 8 8 m s c t f g i n t r i n t e r r u p t ( s e c o n d c o u n t - u p ) i n t e r r u p t ( s e c o n d c o u n t - u p ) w r i t i n g 0 t o c t f g b i t c t f g i n t r 1024hz : t1= 0.977ms 2hz : t1= 500ms
RS5C317A/b 27 11. timer tmout outputs periodic pulses every registered time period (in bank=1, at 9h). setting tmr bit to 1 makes the timer counter reset and possible to operate as a watch-dog-timer. 12. 32khz cloc k output clock signal of 32khz crystal oscillator can be output from the 32kout pin. when this function is disabled the 32kout pin is held at high impedance. 32khz clock output can be controlled through clkc pin and clen pin. * 1) timer counter is available when the ce pin is set 0. * 2) timer function is disabled when the xstp bit is set to 1. (tm 3 to tm 1 and tmcl of timer register become to 0) * 3) refer to ?imer register?in functon section regarding to t1, t2, and t3 in the above figure. * 4) tmout will be off when the tmr bit is set to one with tmout=l (on) * 5) write operation to the timer registers causes starting to operate of timer counter after resetting. * 1) clkc pin incorporates pulled down resistor. * 2) the clen bit will be set to 0 when the xstp bit is set to 1. the conditions of the xstp bit being set to 1 is as follows: (i) initial power-on (ii) supply voltage drop (iii) crystal oscillation halt * 3) do not hold the clkc pin at high level when initial power on. t m r ? 1 t m r ? 1 0 . 9 7 7 m s m a x . t 1 t 2 t 3 t m o u t clkc pin clen bit 32kout output l (open) 0 (disabled to write) high impedance h 0 output 32khz clock h 1 high impedance
RS5C317A/b 28 13. t ypical application * 1) connect the capacitance of the oscillation circuit to the vss pin. * 2) mount the high-and low-frequency by-pass capacitors in parallel and very close to the rs5c317. * 3) connect the pull-up resistor of the intr pin or alrm pin to two different positions depending on whether the resistor is in use during battery back-up: (i) when not in use during battery back-up ............. position a in the above figure (ii) when in use during battery back-up ................... position b in the above figure * 4) when using a ??circuit in place of ?? note that forward voltage of diode should be minimized to eliminate applying excess v oltage to input pins. (take the utmost care on system powering-on and-off). v c c v s s o s c i n o s c o u t v d d v s s v d d d c o r i n t r c e s c l k / s c l k s i o c p u r s 5 c 3 1 7 a / b s y s t e m p o w e r s u p p l y b a s y s t e m p o w e r s u p p l y s y s t e m p o w e r s u p p l y t m o u t a l r m
RS5C317A/b 29 14. t ypical characteristic measurements 14.3 operational current vs. sclk/sclk frequenc y 14.1 standb y current vs. c g 14.2 standb y current vs. v dd 14.4 standb y current vs. t emperature v d d = 3 v v d d = 5 v s t a n d b y c u r r e n t i d d ( a ) t o p t = 2 5 c c g ( p f ) 0 0 . 0 1 . 0 2 . 0 1 0 2 0 3 0 c g = 1 0 p f s t a n d b y c u r r e n t i d d ( a ) t o p t = 2 5 c v d d ( v ) 0 0 . 0 1 . 0 2 . 0 2 4 6 v d d = 3 v v d d = 5 v o p e r a t i o n a l c u r r e n t i o p r ( m a ) t o p t = 2 5 c s c l k / s c l k f r e q u e n c y ( m h z ) 0 . 0 1 0 . 0 0 1 0 . 0 1 0 . 1 1 0 . 1 1 1 0 v d d = 6 v s t a n d b y c u r r e n t i d d ( a ) c g = 1 0 p f t e m p e r a t u r e t o p t ( c ) 6 0 4 0 2 0 0 . 0 1 . 0 2 . 0 0 2 0 4 0 6 0 8 0 1 0 0 v d d = 3 v c g =10pf x'tal : r 1 =30k topt=25?c input pin : vdd or vss output pin : open o s c i n o s c o u t c l k c 3 2 k o u t v s s v d d a c g x ' t a l v d d f r e q u e n c y c o u n t e r
RS5C317A/b 30 14.7 oscillation frequenc y de viation vs. t emperature (f0: t opt=25 c ref erence) 14.5 oscillation frequenc y de viation vs. c g (f0: c g =10pf ref erence) 14.6 oscillation frequenc y de viation vs. v dd (f0: v dd =4v ref erence) 14.8 oscillation star t time vs. v dd o s c i l l a t i o n f r e q u e n c y d e v i a t i o n d f / f 0 ( p p m ) v d d = 3 v , t o p t = 2 5 c c g ( p f ) 0 4 0 2 0 0 2 0 4 0 6 0 8 0 1 0 1 5 5 2 0 2 5 3 0 o s c i l l a t i o n f r e q u e n c y d e v i a t i o n d f / f 0 ( p p m ) c g = 1 0 p f , t o p t = 2 5 c v d d ( v ) 0 4 3 2 1 0 1 2 3 1 4 5 6 o s c i l l a t i o n f r e q u e n c y d e v i a t i o n d f / f 0 ( p p m ) v d d = 3 v , c g = 1 0 p f t e m p e r a t u r e t o p t ( c ) 4 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 0 0 2 0 2 0 4 0 6 0 1 0 0 8 0 c g = 2 0 p f c g = 1 0 p f o s c i l l a t i o n s t a r t t i m e ( s ) t o p t = 2 5 c v d d ( v ) 0 0 . 0 0 . 5 1 . 0 2 3 1 4 5 6 14.9 v ds vs. i ds f or nc h open drain output 14.10 i lh vs. v ih f or clkc pin v d d = 3 v v d d = 5 v n c h o p e n d r a i n o u t p u t i d s ( m a ) t o p t = 2 5 c v d s ( v ) 0 . 0 0 1 0 2 0 3 0 4 0 5 0 1 . 0 1 . 5 0 . 5 2 . 0 i n p u t c u r r e n t i i h ( a ) t o p t = 2 5 c v i h = v d d ( v ) 0 . 0 0 2 4 6 8 1 0 2 . 0 3 . 0 1 . 0 4 . 0 5 . 0 6 . 0
RS5C317A/b 31 ensure stable oscillation by preventing the following: 1) condensation on the crystal oscillator 2) instantaneous disconnection of power 3) generation of clock noises, etc, in the crystal oscillator 4) charge of voltage exceeding prescribed maxi - mum ratings to the individual pins of the ic 15. t ypical software-based operations 15.1 initialization upon p o wer -on 15.2 write operation to cloc k and calendar counter s s t a r t x s t p = 0 ? b s y = 0 ? i n t e r r u p t c y c l e r e g i s t e r ? 0 h c o n t r o l r e g i s t e r 2 ? 3 h ( b a n k ? 1 ) 1 0 - h o u r a l a r m r e g i s t e r ? 0 h ( a l e ? 0 ) c o n t r o l r e g i s t e r 1 ? 3 h c o n t r o l r e g i s t e r 2 ? 1 h , 9 h s e t c l o c k a n d c a l e n d a r c o u n t e r s a n d i n t e r r u p t c y c l e s . w a i t o r o t h e r o p e r a t i o n s . p o w e r - o n y e s n o y e s n o * 1 * 2 * 3 * 4 * 6 * 5 b s y = 0 ? w r i t e t o c l o c k a n d c a l e n d a r c o u n t e r s . c e = l w a i t o r o t h e r o p e r a t i o n s . c e = l c o n t r o l r e g i s t e r 1 ? 0 h c e = h y e s n o * 1 * 2 * 3 * 4 * 1) switch the ce pin to the low level immediately after power-on. * 2) when not making oscillation halt sensing (data validity), the xstp bit need not be checked. * 3) turn off the intr pin, whose output is uncertain at power-on. * 4) set the adj bit to 1. when writing control register 1, if the oscillator has operated, the xstp bit is changed from 1 to 0. * 5) it takes about 0.1 to 2 seconds to be set the bsy bit to 0 from oscillation starting upon power-on from 0v. provide an exit from an oscillation start loop to prepare for oscillation failure. * 6) set the xstp bit to 0 by writing data to the control register 1, and set to the control register 2, 1h for the 12-hour time display system. 9h for the 24-hour time display system. * 1) after switching the ce pin to the high level, hold it at the high level until any subsequent operation requires switching it to the low level. (note that switching the ce pin to the low level sets the wten bit to 1.) * 2) wten bit is set to 0. * 3) the bsy bit is held at 1 for a maximum duration of 122.1 s. * 4) switch the ce pin to the low level to set the wten bit to 1. during write operation to the clock and calendar counters, one 1-second digit carry causes a 1-second increment while two 1-second digit carries also cause only a 1-seconds increment, which, in turn, causes a time delay. when using the xstp bit
RS5C317A/b 32 note 15.3 read operation fr om cloc k and calendar counter s 15.3-1 15.3-3 15.3-2 c t f g = 1 ? r e a d f r o m c l o c k a n d c a l e n d a r c o u n t e r s . i n t e r r u p t o p e r a t i o n f r o m a n y o t h e r i c i n t e r r u p t t o c p u c o n t r o l r e g i s t e r 1 ? 2 h y e s n o * 6 * 7 * 8 b s y = 0 ? r e a d f r o m c l o c k a n d c a l e n d a r c o u n t e r s . c e = l w a i t o r o t h e r o p e r a t i o n s . c e = l c o n t r o l r e g i s t e r 1 ? 0 h c e = h y e s n o * 1 * 2 * 3 * 4 r e a d f r o m c l o c k a n d c a l e n d a r c o u n t e r s . a g a i n r e a d 1 - s e c o n d d i g i t o f c l o c k c o u n t e r . t w o 1 - s e c o n d d i g i t r e a d i n g s m a t c h ? r e a d 1 - s e c o n d d i g i t o f c l o c k c o u n t e r . n o y e s * 5 * 5 * 5 read data as described in 15.3-2 or 15.3-3 when it takes (1/1024) sec or more to set the wten bit from 0 to 1 (ce=l), the read operation described in 15.3-1 is prohibited as such a case. * 1) to * 4) these notes are the same as 15.2 notes * 1) to * 4). * 5) when needing any higher-order digits than the minute digits, replace second digits with minute digits. (reading lsd one of the required digits twice.) * 6) select the level mode as an interrupt mode by setting the ct 3 bit to 1. * 7) write 0 to ctfg bit for turning off intr pin. * 8) complete read operation within an interrupt cycle after interrupt genera - tion. (e.g. within 1 second)
RS5C317A/b 33 c o n t r o l r e g i s t e r 1 ? 3 h * 1 x s t p = 0 ? o s c i l l a t i o n s t a r t w a i t o r o t h e r o p e r a t i o n s . p o w e r - o n c o n t r o l r e g i s t e r 1 ? 2 h y e s n o * 1 * 2 c e ? l a l e ? 1 b a n k ? 1 s e t a l a r m ( h o u r o r m i n u t e , d a y - o f t h e w e e k ) * 1 15.4 write operation to alarm time * 1) non-existent alarm time can set in the alarm registers, but when it sets, an alarm interrupt is disabled. to enable an alarm interrupt, existent alarm time must be set in the alarm registers. 15.5 second-digit adjustment b y 30 seconds * 1) set the adj bit to 1. (the bsy bit is held at 1 for a maximum duration of 122.1 s after the adj bit is set to 1.) 15.6 oscillation star t j udgment * 1) the xstp bit is set to 1 upon power-on from 0v. * 2) it takes approximately 0.1 to 2 seconds to start oscillation. provide an exit from an oscillation start loop to prepare for oscillation failure. ensure stable oscillation by preventing the following: 1) condensation on the crystal oscillator 2) instantaneous disconnection of power 3) generation of clock noises, etc, in the crystal oscillator 4) charge of voltage exceeding prescribed maxi - mum ratings to the individual pins of the ic when using the xstp bit
RS5C317A/b 34 c t f g = 1 ? c y c l i c i n t e r r u p t o p e r a t i o n i n t e r r u p t o p e r a t i o n f r o m a n y o t h e r i c i n t e r r u p t t o c p u c o n t r o l r e g i s t e r 1 ? 2 h s e t i n t e r r u p t c y c l e r e g i s t e r y e s n o * 1 * 2 a l f g = 1 ? a l a r m i n t e r r u p t o p e r a t i o n i n t e r r u p t o p e r a t i o n f r o m a n y o t h e r i c i n t e r r u p t t o c p u a l f g ? 0 s e t a l a r m ( h o u r o r m i n u t e , d a y - o f t h e w e e k ) y e s n o * 1 a l e ? 1 15.7 interrupt operation 15.7-1 cyclic interr upt oper ation 15.7-2 alar m interr upt oper ation * 1) set the interrupt cycle register to the level mode by setting the ct 3 bit to 1. * 2) write 0 to ctfg bit for turning off intr pin. * 1) write 0 to alfg bit for turning off alrm pin.
RS5C317A/b 35 0 . 1 5 + 0 . 1 - 0 . 0 5 0 . 5 0 . 3 0 t o 1 0 0 . 1 0 . 1 0 . 1 5 0 . 1 m 0 . 2 2 0 . 1 1 . 1 5 0 . 1 0 . 5 5 t y p . 0 . 6 5 1 7 6 . 4 0 . 3 4 . 4 0 . 2 1 4 8 5 . 0 0 . 3 0 . 3 2 . 7 m a x . 4 . 0 0 . 1 2 . 0 0 . 0 5 8 . 0 0 . 1 1 . 7 5 0 . 1 5 . 5 0 . 0 5 5 . 4 7 . 0 1 2 . 0 0 . 3 u s e r d i r e c t i o n o f f e e d . 1 . 5 + 0 . 1 0 p a cka ge dimensions (unit: mm) t aping specifica tion (unit: mm) ? RS5C317A/b (14pin ssop) the RS5C317A/b have one designated taping direction. the product designations for the taping components are ?s5c317a-e2?are ?s5c317b-e2?
ricoh company, ltd. electronic devices division headquarters 13-1, himemuro-cho, ikeda city, osaka 563-8501, japan phone +81-727-53-6003 fax +81-727-53-2120 yokohama office (international sales) 3-2-3, shin-yokohama, kohoku-ku, yokohama city, kanagawa 222-8530, japan phone +81-45-477-1697 fax +81-45-477-1694 ?1695 http://www.ricoh.co.jp/lsi/english/ ricoh corporation electronic devices division san jose office 1996 lundy avenue, san jose, ca 95131, u.s.a. phone +1-408-944-3306 fax +1-408-432-8375 http://www.ricoh-usa.com/semicond.htm

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